This invention relates to a semiconductor integrated circuit device which has a reference current generating circuit independent particularly from a power supply voltage Vcc.
FIG. 1 is a circuit diagram showing the conventional reference current generating circuit. In this circuit, a P-channel MOS transistor Qp1, a N-channel MOS transistor Qn1, a resistor R1, and a N-channel MOS transistor Qn2 are connected in series between a power supply voltage Vcc and a ground GND. The gate of the transistor Qp1 is supplied with a starting signal V.sub.start for controlling the circuit to turn from the stand-by state to the active state. The gate of the transistor Qn1 is applied with a reference voltage V.sub.ref generated by the external circuit. The gate of the transistor Qn2 is connected to a drain thereof so as to constitute a diode. The transistor Qn2 outputs an output V.sub.out from the gate to make a reference current I.sub.ref which is equal to the current flowing into Qn2 through the resistor R1, flow from a N-channel MOS transistor Qn6 (Qn6 has substantially the same characteristics and size as those of Qn2) which is connected to form a current mirror circuit with the transistor Qn2.
When the voltages at the both ends of the resistor R1 are respectively denoted as V1 and V2, the current value I.sub.ref is determined by the values of V1 and V2. In the circuit constituted as above, V1 depends on the reference voltage and the threshold voltage of the transistor Qn1, and V2 depends on the threshold voltage of the transistor Qn2. The potentials V1 and V2 are thus determined by the reference voltage V.sub.ref and the threshold voltages V.sub.th of the transistors Qn1 and Qn2, as represented by the following equations: EQU V1=V.sub.ref -V.sub.th EQU V2=V.sub.th (1)
Hence, the current value I.sub.ref is represented as follows: EQU I.sub.ref =(V1-V2)/R1=(V.sub.ref -2V.sub.th)/R1 (2)
where R1 is the resistance value of the resistor R1.
As is clear from the above equation (2), the current value I.sub.ref is represented by the equation which does not include the term of the power supply voltage Vcc. The current value I.sub.ref is determined by the reference voltage V.sub.ref, the threshold voltage V.sub.th of the transistors, and the resistance value R1. This circuit is thus independent from the influence of the power supply voltage Vcc.
FIG. 2 is a circuit diagram showing the constitution of the conventional oscillation circuit using the reference current generating circuit shown in FIG. 1. This circuit is basically the same as that disclosed in U.S. Pat. No. 5,627,488. The elements shown in FIG. 1 are denoted by the same reference numerals.
A capacitor C1 has one end connected selectively to either of the power supply voltage Vcc and the drain of the N-channel MOS transistor Qn6 in accordance with the level of the voltage of the common gate of a N-channel transistor Qn45 and a P-channel transistor Qp20. Similarly, a capacitor C2 has one end connected selectively to either of the power supply voltage Vcc and the drain of the N-channel MOS transistor Qn7 in accordance with the voltage level of the common gate of a N-channel transistor Qn46 and a P-channel transistor Qp21.
P-channel MOS transistors Qp14-Qp16 and N-channel MOS transistors Qn38-Qn40 constitute a first amplifier A1 for comparing the reference voltage V.sub.ref and the voltage V.sub.cap1 at the one end of the capacitor C1 to amplify and output the difference thereof. Similarly, P-channel MOS transistors Qp17-Qp19 and N-channel MOS transistors Qn41-Qn43 constitute a second amplifier A2 for comparing the reference voltage V.sub.ref and the voltage V.sub.cap2 at the one end of the capacitor C2 to amplify and output the difference thereof.
NAND gates G1 and G2 constitute an order logic circuit for outputting the order logic of the two amplifiers. In accordance with the output of the order logic circuit, the voltage level of the common gate of the transistor Qn45 and the transistor Qp20 and the voltage level of the common gate of the transistor Qn46 and the transistor Qp21 are alternately set at "H" (high level) and "L" (low level).
The operation of the oscillation circuit of FIG. 2 will be described below.
In a stand-by state, the signal V.sub.start is set at "H". In this time, the P-channel MOS transistors Qp1, Qp14, Qp17, and the N-channel MOS transistor Qn40 and Qn43 are turned off to shut the power supply system. While, the P-channel MOS transistor Qp13 and the N-channel MOS transistors Qn34, Qn35, and Qn36 are turned on, thereby the circuit is set at an initial state. In this time, the output from the NAND gate G2 is set at "H" and the output from the NAND gate G1 is set at "L". In accordance with the outputs from the NAND gates, the voltage V.sub.cap1 of the one end of the capacitor C1 is set at "L", and the voltage V.sub.cap2 of the one end of the capacitor C2 is set at "H". The output VOSC of the oscillation circuit is thus set at "L".
When the signal V.sub.start is turned from "H" to "L", the oscillation starts: the P-channel MOS transistor Qp13 and the N-channel MOS transistors Qn34, Qn35, and Qn36 are turned off, in contrast, the P-channel MOS transistors Qp1, Qp14, Qp17, and the N-channel MOS transistors Qn40 and Qn43 are turned on. In this time, the reference current generating circuit and the differential amplifiers A1 and A2 are set in the active state.
In the oscillation starting state, V.sub.cap1 is set at "L" with respect to V.sub.ref, and the differential amplifier A1 operates to drop the voltage level of a node N1. The output of the NAND gate G1 is thereby inverted to "H". In contrast, V.sub.cap2 is set at "H" with respect to V.sub.ref, and thus the other differential amplifier A2 operates to increase the voltage level of a node N2 to "H", and the output of the NAND gate G2 is inverted to "L" (in this time, the voltage level of the output signal VOSC of the oscillation circuit is set at "H").
When the NAND gate G1 outputs the signal at "H" level in the above-mentioned manner, the transistor Qn46 is turned on, thereby the capacitor C2 discharges the current I.sub.ref equal to the current flowing through the resistor R1 of the reference current generating circuit. Thus, the voltage level V.sub.cap2 is dropped to a level lower than V.sub.ref, and the potential level of the node N2 is thus dropped to invert the output of the NAND gate G2 to "H" (in this time, the voltage level of the output signal VOSC of the oscillation circuit is set at "L"). While, the NAND gate G2 outputs "L" to turn on the transistor Qp20, and the capacitor C1 is charged to the power supply voltage Vcc. The potential level V.sub.cap1 of the capacitor C1 is thus increased to increase the potential level of the node N1.
In this manner, the levels of G1 and G2 are stabilized at "H" and "L", respectively, during a period from the time when V.sub.cap2 is set at Vcc to the time when V.sub.cap2 is dropped to V.sub.ref.
When the NAND gate G2 outputs "H", the transistor Qn45 is turned on, and the capacitor C1 discharges the current I.sub.ref equal to the current flowing through the resistor R1 of the reference current generating circuit (in this time, the transistors Qn2, Qn6, and Qn7 have substantially the same characteristics and size). The voltage level V.sub.cap1 of the capacitor C1 is dropped to a level lower than V.sub.ref, and the potential level of the node N1 is dropped to invert the output of the NAND gate G1 to "H" (in this time, the voltage level of the output signal VOSC of the oscillation circuit is set at "H").
While, when the NAND gate G1 outputs "L", the transistor Qp21 is turned on, and the capacitor C2 is charged to the power supply voltage Vcc thereby. The potential level V.sub.cap2 of the capacitor C2 is thus increased to increase the potential level of the node N2. As described above, the levels of G1 and G2 are stabilized at "L" and "H", respectively, during a period from the time when the V.sub.cap1 is set at Vcc to the time when V.sub.cap1 is dropped to V.sub.ref. In this manner, the oscillation circuit performs the oscillation by repeating such two states alternatively.
The circuits shown in FIGS. 1 and 2, however, has the problems as described below.
As represented in the equation (2), the circuit shown in FIG. 1 is free from the influence of the power supply voltage. The circuit of FIG. 1, however, depends on the threshold voltages V.sub.th of the transistors Qn1 and Qn2, and thus the reference current is adversely affected by the variation of the threshold voltages of the transistors so much.
Assuming that the variation of the threshold voltage due to the variation generated in the manufacturing process of the transistors is .DELTA.V.sub.th, the average value of the threshold voltage is V.sub.th, the threshold voltage including the variation is V.sub.th ', the relationship among them is represented as V.sub.th '=V.sub.th +.DELTA.V.sub.th. In view of this relationship, the current value I.sub.ref is represented by the following equation: EQU I.sub.ref =(V.sub.ref -2V.sub.th -2.DELTA.V.sub.th)/R1 (3)
The proportion of variation .DELTA.I.sub.ref of the current value I.sub.ref due to the variation .DELTA.V.sub.th of the threshold voltage to the current value I.sub.ref is represented as follows:
.DELTA.I.sub.ref /I.sub.ref =2.DELTA.V.sub.th /(V.sub.ref -2V.sub.th) (4)
When V.sub.ref =2.4V, V.sub.th =0.7V, and .DELTA.V.sub.th =0.2V, the rate of the variation of the current is 0.4/1.0=40%. As is clear from this, the reference current generating circuit shown in FIG. 1 cannot generate the current affected little by the variation of the threshold voltage.
In addition, the oscillation circuit shown in FIG. 2 uses the reference current generating circuit shown in FIG. 1 as a power supply with use of the reference voltage V.sub.ref. In order to prevent he influence of the power supply, the reference voltage V.sub.ref is generally set within a scope from 1.0 to 1.5V. However, if V.sub.ref is decreased, the variation of the current value due to the variation of the threshold voltage will be increased, as represented in the equations (3) and (4). The reference current is deviated larger as V.sub.ref is decreased, even if the variation in the threshold voltage remains the same. In these days, the power supply voltage has been designed to be decreased. This problem therefore will not be ignored.
As described above, the current value I.sub.ref generated by the conventional reference current generating circuit is not affected by the power supply voltage, but is affected by the variation of the threshold voltages of the transistors in the circuit.
The operation of the oscillation circuit using such a reference current generating circuit is inevitably affected by the variation of the reference current value due to the variation of the threshold voltages. Further, even if the variation in the threshold voltage is not increased, the variation in the reference current value will be increased when the reference potential is decreased. Therefore, with such a reference current generating circuit, the reduction of the power supply voltage cannot be easily attained.